1. Field of the Invention
The present invention relates to a solid-state imaging device including an array of pixels for conducting the photoelectric transfer and charge accumulation, and employing a CCD (charge-coupled device), and a method for driving the solid-state imaging device. More particularly, the present invention relates to a solid-state imaging device in which the maximum charge handling capacity is significantly increased.
2. Description of the Related Art
Various types of two-dimensional solid-state imaging devices are known. Among them, a charge-coupled device (CCD) type solid-state imaging device has an advantage that it generates less noise. In general, the CCD type solid-state imaging device is classified into two groups: one group relates to an interline transfer system, and the other group relates to a frame transfer system. At the present time, the CCD type solid-state imaging device of the interline transfer system is most commonly used. This is because such a CCD type solid-state imaging device has practical advantages that it is highly sensitive to short wavelengths, and that it generates less false signals called "smears", and that it can be made small in size.
FIG. 5A schematically shows the structure of a conventional CCD type solid-state imaging device of an interline transfer system. Such a CCD type solid-state imaging device includes a plurality of photosensitive elements (pixels) 1 for converting light into electric charge and accumulating the electric charge. The plurality of pixels 1 are arranged in an array of rows and columns along a first direction (hereinafter, referred to as a vertical direction) and a second direction (hereinafter, referred to as a horizontal direction) which is substantially perpendicular to the first direction. The CCD type solid-state imaging device further includes vertical charge transfer portions 2 each disposed on the adjacent right side of each column of pixels 1 for vertically transferring signals read from the pixels 1, a horizontal charge transfer portion 3 connected to end of each of the vertical charge transfer portions 2 for horizontally transferring the signals supplied from the vertical charge transfer portions 2, and an output portion 4 disposed at one end of the horizontal charge transfer portion 3 for converting the signals supplied from the horizontal charge transfer portion 3 into image signals to output them to an external device.
Each of the vertical charge transfer portions 2 has a four-phase structure. Specifically, each of the vertical charge transfer portions 2 is driven by four-phase driving signals S(1), S(2), S(3), and S(4) which are supplied from an external device. A pair of pixels which are adjacent to each other in the vertical direction correspond to one bit of each of the vertical charge transfer portions 2. For example, the pixels P1 and P2, P3 and P4 correspond to one bit thereof, respectively.
As shown in FIG. 5B, the conventional CCD type solid-state imaging device effects field accumulation and interlaced reading. Specifically, in a first (odd-number) field, signals output from the pixels P1 and P2 which are adjacent to each other in the vertical direction are handled as one packet signal a, while in a second (even-number) field, signals output from the pixels P2 and P3 which are adjacent to each other in the vertical direction are handled as one packet signal a'. Then, in the first field, signals output from the pixels P3 and P4 which are adjacent to each other in the vertical direction are handled as one packet signal b, while in the second field, signals output from the pixels P4 and P5 which are adjacent to each other in the vertical direction are handled as one packet signal b'.
FIG. 6 schematically illustrates a conventional signal processing method used for the CCD type solid-state imaging device mentioned above. In this schematic view, the signal processing for only the first field is shown. The left part of FIG. 6 shows pairs of pixels P1 and P2, P3 and P4, . . . , P15 and P16 arranged in one column along the vertical direction, which respectively output packet signals a, b, . . . , h. The right part of FIG. 6 shows an arrangement of the packet signals a, b, . . . , h in one of the vertical charge transfer portions 2 in the time sequence.
FIG. 7 shows a potential distribution of the electrodes of one of the vertical charge transfer portions 2 in time sequence in order to illustrate the signal transfer in the vertical charge transfer portion 2.
Referring to FIG. 7, in stage (1), all of the signals a1, a2, b1, b2, . . . formed in the pixels P1, P2, P3, P4, . . . in one column are simultaneously read into the vertical charge transfer portion 2. Then, in stage (2), each two signals a1 and a2, b1 and b2, . . . read from the pairs of pixels P1 and P2, P3 and P4, . . . are added together to obtain signals (a1+a2), (b1+b2), . . . which corresponds to one bit of the vertical charge transfer portion 2, respectively.
In stage (3) and as shown in FIG. 6, all the signals present in the vertical charge transfer portion 2 are vertically shifted by one bit, so that the signal (a1+a2), i.e., a first packet signal a is transferred into the horizontal charge transfer portion 3. Hereinafter, a packet signal is referred to as a signal read from a unit of pixels, for example, a pair of pixels P1 and P2. The transferred packet signal a is then horizontally transmitted in the horizontal charge transfer portion 3 at high speed to reach the output portion 4, where it is converted into an image signal and is output to an external device.
After the first packet signal a is processed as described above, in stage (4), a signal (b1+b2) corresponding to the next single bit of the vertical charge transfer portion 2, i.e., a second packet signal b is transferred into the horizontal charge transfer portion 3. The transferred packet signal b is then horizontally transmitted in the horizontal charge transfer portion 3 at high speed to reach the output portion 4, where it is converted into an image signal and is output to an external device.
A third packet signal c (stage (5)), a fourth packet signal d (stage (6)), and other subsequent packet signals are also processed as described above. The horizontal charge transfer portion 3 transmits each signal corresponding to one bit of the vertical charge transfer portion 2 to the output portion at high speed whenever it receives the signal. The output portion 4 then converts the signal into an image signal and outputs it into an external device.
Thus, as shown in FIG. 6, the packet signals each corresponding to a single bit of the vertical charge transfer portion 2 are transferred one by one into the horizontal charge transfer portion 3 during the respective horizontal scanning periods 1H, and then are output from the output portion 4.
According to the conventional CCD type solid-state imaging device mentioned above, one packet signal corresponds to only one bit of the vertical charge transfer portion 2. This means that the maximum charge handling capacity which the vertical charge transfer portion 2 can handle is limited to the capacity available for one bit thereof. Since a dynamic range of such a solid-state imaging device depends on the maximum charge handling capacity, the dynamic range of the solid-state imaging device is limited when the maximum charge handling capacity is limited to a certain capacity. This may result in causing a problem when it is desirable to provide a small-sized solid-state imaging device.
To solve such a problem, two types of transfer methods are disclosed in Japanese Laid-Open Patent Publication No. 60-119182 (FIG. 8A) and Japanese Laid-Open Patent Publication No. 60-183881 (FIG. 8B), respectively. These methods, both called a charge sweep method, include the steps of reading one packet signal, spreading it over a vertical charge transfer portion, and collecting a charge of the signal into a storage portion which is provided at one end of the vertical charge transfer portion during one horizontal transfer period. Regarding how to collect the charge of the signal into the storage portion, one method shown in FIG. 8A includes the steps of gradually enlarging a potential barrier X. The other method shown in FIG. 8B includes the step of splitting the charge of the signal into a plurality of wells Y and transferring it a plurality of times.
According to the transfer methods mentioned above, the a charge handling capacity corresponding to one image signal capable of being handled by the vertical charge transfer portion greatly increases. However, the following problems arise: the operation of collecting the charge of the signal which is read from pixels to the vertical charge transfer portion into one end of the vertical charge transfer portion is carried out during a time period when the horizontal charge transfer portion is operating to transfer the charge of the signal to an output portion, that is, an image signal is being output. As a result, driving pulse signals for driving the vertical charge transfer portion may be intruded into the image signal, resulting in generating noise. Further, since the charge of the signal is collected from the entire portion of the vertical charge transfer portion into the storage portion provided at one end thereof, the number of driving pulse signals required for the operation of this collection increases, resulting in an increase in power consumption.